A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC: Bare-Metal Fundamentals

The Xilinx Zynq-7000 Adaptive SoC defined a radical shift in the embedded engineering world when it was introduced in 2011, combining the hardware programmability of a Xilinx 7-Series FPGA with the software programmability of an ARM Cortex-A9 MPCore on a single chip. The compelling advantages of such a formidable device come at the cost of increased complexity, however, and up to now a high-caliber introductory book has not been written which provides a clear, accessible starting point for the (budding) engineer. A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC: Bare-Metal Fundamentals solves this problem by focusing on the bare-metal development flow, which is the best way to become familiar with the device. The book is broadly split into three sections, covering the following topics:

Hardware Technology

• Extensive history of embedded processor solutions in Xilinx FPGAs, and a comprehensive introduction to the Zynq-7000 Adaptive SoC.
• Arm processor fundamentals- ARM7TDMI technology (for introductory purposes), ARMv7A architecture, and ARM Cortex-A9 MPCore.
• Zynq-7000 architecture in detail- APU, PS, and Xilinx 7-Series FPGA Technology.
• Detailed overview of the Digilent Zybo-Z7-20 development board.

Bare-Metal Development Flow

• Summary of FPGA design techniques, along with step-by-step planning and implementation of the FPGA design used for the software projects in the text.
• Comprehensive overview of hardware hand-off, software development in Xilinx SDK, plus an introduction to the Vitis unified software platform.
• Thorough explanation of Xilinx device driver architecture, and an introduction to Xilinx Software Command-Line Tool.
• Comprehensive overview of the project deployment stage (SD Card and QSPI system boot).

Software Projects

• Structured Programming in C- A layered hierarchy is established which makes it much easier to develop and scale bare-metal applications for the Zynq-7000.
• Processing System and Programmable Logic GPIO; Cortex-A9 MPCore timers and watchdogs; APU Triple Timing Counter; Switch debouncing.
• Comprehensive description of the Zynq-7000 interrupt system.
• Complete details for the design of a fully decoupled embedded command handler.
• Host PC application design, where Python and LabVIEW are used to interact with the embedded command handler.
• Software development for the AXI GPIO and AXI Quad SPI blocks implemented on the FPGA, including interrupt handling for the programmable logic.
• Additional interrupt topics- Nested interrupt handling, and protection of shared variables in critical sections of code.

The concepts related to each project are discussed in detail, and the embedded C-code is thoroughly explained (and freely available on GitHub). Other comprehensive support material includes step-by-step documents describing the FPGA design in IP Integrator, followed by the implementation of each project in Xilinx SDK or Vitis IDE. The Digilent Zybo-Z7-20 is used as the target platform in the text, although the code can be easily modified for use on other Zynq-7000 development boards.

GitHub link for supplementary material: https://github.com/der-mur/book1-zynq-intro